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ADT7518
 
Rev. A | Page 5 of 40
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DIGITAL OUTPUT
 
 
 
 
 
Digital High Voltage, V
OH
2.4
 
 
V
I
SOURCE
 = I
SINK
 = 200 礎.
Output Low Voltage, V
OL
 
 
0.4
V
I
OL
 = 3 mA.
Output High Current, IOH
 
 
1
mA
VOH = 5 V.
Output Capacitance, COUT
 
 
50
pF
 
INT/INT
 Output Saturation Voltage   
 
0.8
V
IOUT = 4 mA.
I
2
C TIMING CHARACTERISTICS
8,
 
9
 
 
 
 
 
Serial Clock Period, t1
2.5
 
 
祍
Fast Mode I
2
C. See Figure 2.
Data In Setup Time to SCL High, t
2
50
 
 
ns
 
Data Out Stable after SCL Low, t
3
0
 
 
ns
See Figure 2.
SDA Low Setup Time to SCL
Low (Start Condition), t4
50
 
 
ns
See Figure 2.
SDA High Hold Time after SCL
High (Stop Condition), t5
50
 
 
ns
See Figure 2.
SDA and SCL Fall Time, t
6
 
 
90
ns
See Figure 2.
SPI TIMING CHARACTERISTICS
4,
 
10
 
 
 
 
 
CS
 to SCLK Setup Time, t1
0
 
 
ns
See Figure 3.
SCLK High Pulse Width, t
2
50
 
 
ns
See Figure 3.
SCLK Low Pulse Width, t
3
50
 
 
ns
See Figure 3.
Data Access Time after SCLK
Falling Edge, t4
11
 
 
35
ns
 
Data Setup Time Prior to SCLK
Rising Edge, t
5
20
 
 
ns
See Figure 3.
Data Hold Time after SCLK Rising
Edge, t
6
0
 
 
ns
See Figure 3.
CS
 to SCLK Hold Time, t7
0
 
 
祍
See Figure 3.
CS
 to DOUT High Impedance, t8
 
 
40
ns
See Figure 3.
POWER REQUIREMENTS
 
 
 
 
 
VDD
2.7
 
5.5
V
 
VDD Settling Time
 
 
50
ms
VDD settles to within 10% of its final voltage level.
IDD (Normal Mode)
12
 
 
3
mA
VDD = 3.3 V, VIH = VDD, and VIL = GND.
 
 
2.2
3
mA
V
DD
 = 5 V, V
IH
 = V
DD
, and V
IL
 = GND.
I
DD
 (Power-Down Mode)
 
 
10
礎
V
DD
 = 3.3 V, V
IH
 = V
DD
, and V
IL
 = GND.
 
 
 
10
礎
V
DD
 = 5 V, V
IH
 = V
DD
, and V
IL
 = GND.
Power Dissipation
 
 
10
mW
VDD = 3.3 V. Normal mode.
 
 
 
33
礧
VDD = 3.3 V. Shutdown mode.
 
 
1
 See the
 section.
 Terminology
2
 DC specifications are tested with the outputs unloaded.
3
 Linearity is tested using a reduced code range: ADT7518 (Code 8 to 255).
4
 Guaranteed by design and characterization, not production tested.
5
 Round robin is the continuous sequential measurement of the following channels: V
DD
, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.
6
 The temperature accuracy specifications are valid when the internal reference is not being used by the on-chip DAC. For new designs, the ADT7519 is recommended
as it does not have this limitation.
7
 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset
plus gain error must be positive.
8
 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I
2
C specification. Switching off the input filters improves the transfer rate
but has a negative effect on the EMC behavior of the part.
9
 Guaranteed by design, not production tested.
10
 All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
), and timed from a voltage level of 1.6 V.
11
 Measured with the load circuit shown in Figure 4.
12
 The I
DD
 specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.
 
 
 
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